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QR
- QR分解是球形MIMO检测算法必不可少的环节,本代码采用m语言描述了QR分解分解具体怎么实现,而不是直接调用matlab内部函数,采用的是QR分解的脉动阵列结构,据此代码可轻易实现QR分解的FPGA设计-QR decomposition is an essential part of the spherical MIMO detection algorithm, the code uses QR decomposition decomposition m language to describe
assignment
- FPGA assignment for M. Tech Students to solve
PFGA-frequency--
- 用FPGA实现高频高精度的外部频率检测，并用1602液晶屏显示频率，用Cyclone II EP2C35F672C8N 型号的FPGA 可实现检测高达1.5M HZ的输入频率，对应的精度只有百分之0.5。-Using FPGA to realize external frequency detection with high frequency and high precision,and use 1602 LCD screen display frequency, using the Cyc
mseq
- 在fpga开发板上运行，生产m序列。 包括m1.v为主文件，mtest.v是测试文件，用于modelsim 仿真-In fpga development board to run the production m sequence. Including m1.v primary file, mtest.v is a test file for modelsim simulation
mPsequences
- m序列信号发生，用verilog编写，在fpga上可实现-m sequences
cos_value
- 用于生成FPGA中RAM所需要的初始化文件dds.mif,此文件生成的是余弦波形。-This document of .m can generate document of .mif to provide data for RAM of FPGA.
sdram_ov7670_rgb565
- VGA显示，相当给力，采用FPGA实现的，我使用的是OV7670摄像头采集数据的-VGA display, quite a force, using FPGA, and I' m using OV7670 camera data acquisition
RANGEN
- 2011年全国大学生电子设计竞赛E题“简易数字信号传输性能分析仪”fpga的控制代码，verilog编写；包括了M序列及同步时钟的提取等所有程序。-2011 National Undergraduate Electronic Design Contest E title "Simple digital signal transmission performance analyzer" fpga control code, verilog prepared including the M-seq
Verilog
- 七段数码管译码器.(Verilog)[FPGA]第一个Verilog程序,七段共阴数码管摸索了好几天,终于能完成敲入代码、综合、仿真、绑定引脚至下载的全套工作了 -. 七段数码管的lookup table module SEG7_LUT ( input [3:0] iDIG, output reg [6:0] oSEG ) always@(iDIG) begin case(iDIG) 4 h1: oSEG = 7 b1111
_Binary-File-Reader
- I m Labview Programer Want send fpga samples for labview
Mxulie
- VHDL语言编写，利用FPGA实现的M序列发生器-VHDL language, FPGA realization of the M sequence generator
dds(9854)_test(sin_cos)(EP1C6)
- 通过FPGA控制DDS(AD9854)输出120M一下的双路正交信号，实现在通信和控制领域的应用。-Controlled by FPGA DDS (AD9854) output 120 m the dual orthogonal signal, realize the application in the field of communication and control.
FPGAluojidaima
- 16通道逻辑分析仪，100M，FPGA代码，包括FIFO，dram，usb等-16 channel logic analyzer, 100 m, the FPGA code, including FIFO, DRAM, usb, etc
ethernet_tri_mode
- FPGA 10M/100M/1000M以太网IP核源码，外接88e1111phy芯片进行了仿真验证，对FPGA 以太网MAC层开发人员非常有用-The FPGA 10 m/100 m/1000 m Ethernet IP core source code, an external 88 e1111phy chip simulation verification, is very useful for developers FPGA Ethernet MAC layer
m_counter
- this project about compteur m bit compiled and implanted in cart fpga xilinx 3E, with file .HDL and .bit
pts_papr_simula_implemantation
- ABSTRACT In this paper, the design and implementation of OFDM system along with Multi-Point Square Mapping combined with PTS (M-PTS) technique has received much attention in reducing the high peak to average power ratio (PAPR) of Orthogonal Frequen
ADC
- verilog At the last, before starting fist go through the FPGA NEXYS2 Board manual. It will be useful for you for this interfacing and also for the future. Best of luck…, try this one because practice makes man perfect. And, yes also if you have a
3M
- 在FPGA实验操作系统实现ASK,FSK,PSK的调制解调，基带信号由M序列发生器产生，经过AD模块在示波器上进行显示，精油DA模块在同一块实验板上进行解调操作，生成信号控制LED灯的亮灭，并与调制输出信号在示波器上同时展示，并进行对比。基带信号为3MHz。(In the FPGA operating system experiment implementation ASK, FSK, PSK modulation and demodulation of the baseband signal